1. Field of the Invention
The invention relates to semiconductor device fabrication and, more particularly, to a method and apparatus for incorporating low dielectric constant materials within a multilevel metallization and interconnect structure.
2. Description of the Background Art
The integrated circuit industry is moving towards denser device integration and faster switching speeds for devices within the integrated circuits. Until recently, the integrated circuit R-C delay that limits the device switching speeds was dominated by the front-end-of-line (FEOL) CMOS transistor driver capacitance and load resistance. For 0.25 um technology and beyond, the increase in signal delay due to the capacitance of device interconnections is becoming a limitation to improving device performance. To meet circuit speed requirements and to decrease crosstalk between adjacent metal interconnection lines, devices must be fabricated using materials having low dielectric constants (e.g., less than 3.8). In present integrated circuit manufacturing, silicon-dioxide (SiO.sub.2), having a dielectric constant of approximately 4.0, is generally used as an insulative material. However, a material with such a relatively high dielectric constant does not meet the speed requirements of today's devices and such materials promote excessive signal crosstalk between adjacent interconnection lines.
Alternative materials having lower dielectric constants than SiO.sub.2 include fluorinated silicate glass (FSG), having a dielectric constant between 3.5 and 3.8, as well as amorphous-fluorinated carbon (a-C:F), having a dielectric constant of less than 3.0. Additionally, various fluorinated organic or inorganic, spin-on or vapor deposited dielectric materials, such as fluorinated polyimide, fluorinated poly arylene ethers, parylene-F, and the like, have also been used within integrated circuits as relatively low dielectric constant materials. All of these materials are generally classified as "low k materials" when the dielectric constant (k) is less than 3.8 or "ultra-low k materials" when the dielectric constant (k) is less than 3.0. In this specification, these terms are used interchangeably and represent materials with a dielectric constant less than 4.0.
One process for producing a relatively low k material is by incorporating fluorine, with 2-3 atomic percent to as much as 40 percent, within a base material of silicon dioxide or amorphous carbon to form F--SiO.sub.2 or a-C:F, respectively. However, a major problem with integrating these materials into a metallized structure, e.g., a BEOL structure, is that the fluorine corrodes metals such as titanium or aluminum-copper that are typically used for metallization of the integrated circuits. For example, titanium is an integral part of a BEOL metallization process and helps to decrease the interface resistance at the via bottom. However, when titanium is integrated into a fluorine-based oxide, numerous volcanoes are generated on the titanium surface. This volcano formation is due to corrosion of the titanium by the fluorine within the F--SiO.sub.2 Such volcanoes cause a decrease in device reliability within the integrated circuit, as well as drastically reduce the lifetime of the device.
Fluorinated oxide deposited using a high-density plasma, where the fluorine is more tightly bonded to the silicon oxide, also has similar problems during integration with metals. In such structures, the fluorine level in the bulk titanium is an order of magnitude higher than the background level in an undoped film. This indicates the fluorine penetrates into the titanium layer deposited on top of the dielectric. Such penetration can lead to an increase in the via/contact resistance, and device failures due to corrosion. Similar problems arise when using aluminum-copper (AlCu) alloys for metallization.
FIGS. 1A through 1D depict a conventional process for producing a BEOL metallization structure. Within the structure, the metals detrimentally contact the dielectric during dielectric deposition and also during metal deposition when performing the plug and/or the interconnect metallization. Specifically, FIG. 1A depicts a pair of metal lines 102 that have been formed on a substrate 100 using either a PVD process to deposit a layer 110 and 112 of titanium or titanium nitride above and below an aluminum-copper conductive layer 114. These lines are generally formed by pattern etching a uniformly deposited stack of metal layers to form the structure shown in FIG. 1A. In FIG. 1B, a low k dielectric material (low k material) is deposited as a layer 104 atop the lines. Note that in this conventional process the metal lines contact the dielectric material of layer 104. In FIG. 1C, a second dielectric layer 116 (e.g., TEOS) is deposited over layer 104. The second dielectric layer is planarized using, for example, a chemical-mechanical polishing process. The second dielectric layer is patterned using a mask and both dielectric layers are etched to form a via 106. Generally, the etch process removes some of the metal material at the bottom of the via to ensure a sufficiently conductive contact will be made between the metal line and the via metallization, e.g., the etch is stopped upon contact with the aluminum-copper layer. In FIG. ID, titanium/titanium-nitride is deposited as a liner 108 to contact the top surface of the metal lines 102. The liner in the via is subsequently filled with aluminum-copper or tungsten.
Within the foregoing conventional process, the metal contacts the low k dielectric when the first dielectric layer is deposited over the metal lines. When the first dielectric material is a fluorine-based, low k material, the metal reacts with the dielectric and detrimentally corrodes. The potential for such corrosion is apparent in the SIMS depth profile of FIG. 2. The SIMS depth profile shows that, when a low k dielectric layer (F--SiO.sub.2) is contacted by a titanium layer within a Ti/HDP-FSG stack and annealed at 450.degree. C., as shown in the fluorine concentration curve 200, the fluorine substantially penetrates into the titanium.
Therefore, a need exists in the art for a method and apparatus for fabricating multilevel metallization and interconnect structures that prevent metal corrosion when using low k dielectric materials as insulators.